DieTY extends EoI date for setting up semiconductor fab

The government of India has extended the last date for Expression of Interest (EoI) for setting up of semiconductor fab manufacturing facility in the country.

The Department of Electronics and Information Technology (DeiTY) has extended the date to November 25, 2013 as the last date for submitting EoI by semiconductor wafer fabrication (fab) manufacturers for establishing fab manufacturing facilities in India. Earlier the last date was 6th November, 2013.

In order to attract large number of semiconductor fab manufacturers from all over the globe, the government of India had recently decided to apprise all manufacturers of the quantum of subsidy/other benefits/support being offered for establishing fab manufacturing facilities in India.

Last month, the government had accorded ‘in principle’ approval for establishing two fab manufacturing facilities in the country and issued letters of ‘in principle’ approval to the 2 bidders.

The technical requirements, the structure of incentives, the requirement of equity structure and other terms are indicated in the format for Expression of Interest (EoI) available on the website of DeiTY.

Recebtly, the Indian government has approved setting up of two semicon fab manufacturing facilities in the country worth Rs 51,550 crore.

Jaiprakash Associates and Hindustan Semiconductor Manufacturing are the two consortiums approved by government of India for semicon fab. Both these facilities are expected to provide a big boost to the electronics system design and manufacturing eco-system in the country.

Jaiprakash Associates has tied up with IBM, US and Tower Jazz, Israel for semicon fab. The outlay of the proposed FAB is about Rs 26,300 crore and will manufacture 40,000 wafers per month of 300 mm size, using advanced CMOS technology. In phase I, the fab will focus on 90, 65 and 45 nm node, phase II will focus on 28 nm node and phase III will focus on 22 nm node. The proposed location for Jaiprakash Associates is Greater Noida.

Hindustan Semiconductor Manufacturing (HSMC) has tied up with ST Microelectronics, France and Silterra, Malaysia for semicon fab. The outlay of the proposed FAB is about Rs 25,250 crore for the fab facility of 40,000 wafer starts per month of 300 mm size, using advanced CMOS technology. Technology nodes proposed are 90, 65 and 45 nm nodes in Phase I; and 45, 28 and 22 nm nodes in Phase II. The proposed location for HSMC is Prantij, near Gandhinagar, Gujarat.

Leave a Reply

%d bloggers like this: